The invention relates to a method to enhance grain size in polycrystalline silicon, called polysilicon. Larger grain size in polysilicon is advantageous for many uses, particularly in thin film transistors (TFTs).
One of the major obstacles to the use of polysilicon thin film as a semiconductor in active devices is the relatively small grain sizes (around 0.05 micron or less) of polysilicon thin films deposited by such methods as low-pressure chemical vapor deposition and sputtering. A film with small grain size has a larger number of grain boundaries, decreasing carrier mobility. Typical electron mobilities in polysilicon films made using these methods are on the order of 10 cm2/volt-second, two orders of magnitude lower than electron mobilities in bulk silicon.
The poor electrical performance caused by grain boundaries in the channel region limits the use of TFTs largely to low-temperature flat panel displays. It is believed that electrical properties of TFTs can be improved if the grain size is enhanced and the number of grain boundaries in the channel region minimized.
It is known to seed amorphous silicon with a crystallizing agent to induce crystallization, followed by an anneal to increase grain size. For example, Gu, U.S. patent application Ser. No. 10/391,142, “Large Grain Size Polysilicon Films Formed by Nuclei-Induced Solid Phase Crystallization,” filed Mar. 17, 2003, hereby incorporated by reference, uses silicon nuclei as a crystallizing agent. This is a method to produce large grains by seeding. A first amorphous silicon layer is formed. Silicon nuclei are deposited, and crystallization is prevented until a second amorphous silicon layer is formed. The wafer is then annealed to form a polysilicon layer. As described in Gu, this method prevents hemispherical grain formation, producing a layer of large-grained silicon grains particularly advantageous for formation of TFT transistor channels.
In the method of Gu, however, placement of the silicon nuclei is not controlled. A grain grows from each nucleus. While overall grain size is increased with this method, in specific locations, if two or more silicon nuclei happen to be deposited very close to each other, there may be a higher concentration of grain boundaries relative to other areas. Similarly, if other areas see a lower-than average distribution of silicon nuclei, those areas may require a long anneal time to ensure that no amorphous silicon remains between grains. The difference in local nucleus densities is one cause of non-uniformity of thin film transistors across a wafer in production. Minimizing the difference in local nucleus densities across a wafer will improve the uniformity of thin film transistors built on such a wafer and achieve a better production yield.
Oh et al., “A Proposed Single Grain-Boundary Thin-Film Transistor,” IEEE Electronic Device Letters, Vol. 22, No. 1, January 2001, attempt to control the number of grain boundaries in a transistor channel by providing two nucleation sites for each transistor, one where the source will be formed and one where the drain will be formed. An anneal causes a grain to grow from each nucleation site, until the two grains abut, thus guaranteeing that there will be exactly one grain boundary in the channel.
Placement of seeds at source and drain for every transistor according to Oh et al., while practicable for a single transistor or a small number of transistors, becomes expensive and cumbersome for an array of transistors, particularly when device size is small. In production this method could become prohibitively expensive due to circuit layout and mask layout changes required for different products and design modifications.
There is a need, therefore, for a low-cost, practical method to enhance grain size and grain uniformity in polysilicon thin films.